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? semiconductor components industries, llc, 2013 april, 2013 ? rev. 10 1 publication order number: mc14001b/d mc14001b series b-suffix series cmos gates mc14001b, mc14011b, mc14023b, mc14025b, mc14071b, mc14073b, mc14081b, mc14082b the b series logic gates are constructed with p and n channel enhancement mode devices in a single monolithic structure (complementary mos). their primary use is where low power dissipation and/or high noise immunity is desired. features ? supply voltage range = 3.0 vdc to 18 vdc ? all outputs buffered ? capable of driving two low ? power ttl loads or one low ? power schottky ttl load over the rated temperature range. ? double diode protection on all inputs except: triple diode protection on mc14011b and mc14081b ? pin ? for ? pin replacements for corresponding cd4000 series b suffix devices ? these devices are pb ? free and are rohs compliant ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ? 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ? 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ? 55 to +125 c t stg storage temperature range ? 65 to +150 c t l lead temperature (8 ? second soldering) 260 c v esd esd withstand voltage human body model machine model charged device model > 3000 > 300 n/a v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. device description device information mc14001b quad 2 ? input nor gate mc14011b quad 2 ? input nand gate mc14023b triple 3 ? input nand gate mc14025b triple 3 ? input nor gate mc14071b quad 2 ? input or gate marking diagrams 1 14 pdip ? 14 p suffix case 646 mc140xxbcp awlyywwg soic ? 14 d suffix case 751a tssop ? 14 dt suffix case 948g 1 14 140xxbg awlyww 14 0xxb alyw 1 14 xx = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package mc14073b triple 3 ? input and gate mc14081b quad 2 ? input and gate mc14082b dual 4 ? input and gate see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information http://onsemi.com (note: microdot may be in either location)
mc14001b series http://onsemi.com 2 logic diagrams 1 2 5 6 8 9 12 13 3 4 10 11 1 2 5 6 8 9 12 13 3 4 10 11 1 2 5 6 8 9 12 13 3 4 10 11 1 2 5 6 8 9 12 13 3 4 10 11 2 input 1 2 9 3 input 8 3 4 6 5 11 12 10 13 1 2 9 8 3 4 6 5 11 12 10 13 1 2 9 8 3 4 6 5 11 12 10 13 1 13 3 4 5 2 10 11 12 9 nc = 6, 8 v dd = pin 14 v ss = pin 7 for all devices nor mc14001b quad 2 ? input nor gate mc14025b triple 3 ? input nor gate mc14023b triple 3 ? input nand gate nand mc14011b quad 2 ? input nand gate or mc14071b quad 2 ? input or gate and mc14081b quad 2 ? input and gate mc14073b triple 3 ? input and gate mc14082b dual 4 ? input and gate pin assignments 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c out d in 1 d in 2 d v dd in 1 c in 2 c out b out a in 2 a in 1 a v ss in 2 b in 1 b 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c out d in 1 d in 2 d v dd in 1 c in 2 c out b out a in 2 a in 1 a v ss in 2 b in 1 b 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c in 1 c in 2 c in 3 c v dd in 3 a out a in 2 b in 1 b in 2 a in 1 a v ss out b in 3 b 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c in 1 c in 2 c in 3 c v dd in 3 a out a in 2 b in 1 b in 2 a in 1 a v ss out b in 3 b 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c out d in 1 d in 2 d v dd in 1 c in 2 c out b out a in 2 a in 1 a v ss in 2 b in 1 b 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c in 1 c in 2 c in 3 c v dd in 3 a out a in 2 b in 1 b in 2 a in 1 a v ss out b in 3 b 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c out d in 1 d in 2 d v dd in 1 c in 2 c out b out a in 2 a in 1 a v ss in 2 b in 1 b 11 12 13 14 8 9 10 5 4 3 2 1 7 6 in 2 b in 3 b in 4 b out b v dd nc in 1 b in 3 a in 2 a in 1 a out a v ss nc in 4 a nc = no connection mc14023b triple 3 ? input nand gate mc14001b quad 2 ? input nor gate mc14011b quad 2 ? input nand gate mc14082b dual 4 ? input and gate mc14081b quad 2 ? input and gate mc14025b triple 3 ? input nor gate mc14071b quad 2 ? input or gate mc14073b triple 3 ? input and gate
mc14001b series http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) ?????????? ?????????? ?????????? characteristic ???? ???? ???? ??? ??? ??? ????? ????? ? 55 c ????????? ????????? c ????? ????? c ??? ??? ??? ??? ??? ??? ??? ???? ???? ??? ??? ???? ???? ??? ??? ??? ??? ?????????? ?????????? ?????????? output voltage ?0? level v in = v dd or 0 ???? ???? ???? ??? ??? ??? ??? ??? ??? ? ? ? ??? ??? ??? 0.05 0.05 0.05 ???? ???? ???? ? ? ? ??? ??? ??? 0 0 0 ???? ???? ???? ??? ??? ??? ? ? ? ??? ??? ??? 0.05 0.05 0.05 ??? ??? ??? ?????????? ?????????? ?????????? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 4.95 9.95 14.95 ??? ??? ??? ???? ???? ???? ? ? ? ??? ??? ??? 4.95 9.95 14.95 ??? ??? ??? ? ? ? ??? ??? ??? vdc ?????????? ?????????? ?????????? ?????????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ??? ??? ??? ??? 1.5 3.0 4.0 ???? ???? ???? ???? ? ? ? ??? ??? ??? ??? 2.25 4.50 6.75 ???? ???? ???? ???? ??? ??? ??? ??? ? ? ? ??? ??? ??? ??? 1.5 3.0 4.0 ??? ??? ??? ??? ?????????? ?????????? ?????????? ?????????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? ???? 3.5 7.0 11 ??? ??? ??? ??? ???? ???? ???? ???? ? ? ? ??? ??? ??? ??? 3.5 7.0 11 ??? ??? ??? ??? ? ? ? ??? ??? ??? ??? vdc ?????????? ?????????? ?????????? ?????????? ?????????? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ? 2.4 ? 0.51 ? 1.3 ? 3.4 ??? ??? ??? ??? ??? ???? ???? ???? ???? ???? ? ? ? ? ??? ??? ??? ??? ??? ? 1.7 ? 0.36 ? 0.9 ? 2.4 ??? ??? ??? ??? ??? ? ? ? ? ??? ??? ??? ??? ??? madc ?????????? ?????????? ?????????? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ? ? ???? ???? ???? 0.51 1.3 3.4 ??? ??? ??? ???? ???? ???? ? ? ? ??? ??? ??? 0.36 0.9 2.4 ??? ??? ??? ? ? ? ??? ??? ??? madc ?????????? ?????????? ???? ???? ??? ??? ??? ??? ? ??? ??? 0.1 ???? ???? ? ??? ??? 0.00001 ???? ???? 0.1 ??? ??? ? ??? ??? 1.0 ??? ??? adc ?????????? ?????????? ?????????? ???? ???? ???? ??? ??? ??? ? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? 5.0 ???? ???? ???? ??? ??? ??? ? ??? ??? ??? ??? ??? ??? pf ?????????? ?????????? ?????????? ???? ???? ???? ??? ??? ??? ??? ??? ??? ? ? ? ??? ??? ??? 0.25 0.5 1.0 ???? ???? ???? ? ? ? ??? ??? ??? 0.0005 0.0010 0.0015 ???? ???? ???? ??? ??? ??? ? ? ? ??? ??? ??? 7.5 15 30 ??? ??? ??? adc ?????????? ?????????? ?????????? ?????????? ???? ???? ???? ???? ??? ??? ??? ??? ????????????????? ????????????????? ????????????????? ????????????????? a/khz) f + i dd /n i t = (0.6 a/khz) f + i dd /n i t = (0.9 a/khz) f + i dd /n ??? ??? ??? ??? adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.001 x the number of exercised gates per package.
mc14001b series http://onsemi.com 4 b ? series gate switching times ????????????????????????????????? (c l = 50 pf, t a = 25 c) ??????????????? ??????????????? ??????????????? characteristic ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? output rise time, all b ? series gates t tlh = (1.35 ns/pf) c l + 33 ns t tlh = (0.60 ns/pf) c l + 20 ns t tlh = (0.40 ns/pf) c l + 20 ns ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ? ? ? ???? ???? ???? ???? 100 50 40 ???? ???? ???? ???? ??? ??? ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? ? series gates t thl = (1.35 ns/pf) c l + 33 ns t thl = (0.60 ns/pf) c l + 20 ns t thl = (0.40 ns/pf) c l + 20 ns ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ? ? ? ???? ???? ???? ???? 100 50 40 ???? ???? ???? ???? ??? ??? ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ??????????????? ? input gates (mc14068b, mc14078b) t plh , t phl = (0.90 ns/pf) c l + 155 ns t plh , t phl = (0.36 ns/pf) c l + 62 ns t plh , t phl = (0.26 ns/pf) c l + 47 ns ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ? ? ? ? ? ? ? ? ? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 125 50 40 160 65 50 200 80 60 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. v dd 14 c l v ss 7 pulse generator input output 90% 50% 10% 10% 50% 90% 20 ns 20 ns t phl t plh t tlh t thl v ol v oh 0 v v dd input output inverting *all unused inputs of and, nand gates must be connected to v dd . all unused inputs of or, nor gates must be connected to v ss . 90% 50% 10% v ol v oh output non-inverting t thl t tlh t plh t phl * figure 1. switching time test circuit and waveforms
mc14001b series http://onsemi.com 5 circuit schematic nor, or gates 14 * 7 v ss 3, 4, 10, 11 v dd v ss v dd *inverter omitted in mc14001b 1, 6, 8, 13 2, 5, 9, 12 14 * 7 9, 6, 10 v ss v dd 1, 3, 11 2, 4, 12 v ss v dd v ss v dd 8, 5, 13 mc14001b, mc14071b one of four gates shown mc14025b one of three gates shown *inverter omitted in mc14025b circuit schematic nand, and gates 14 * 7 3, 4, 10, 11 v ss v dd *inverter omitted in mc14011b 14 * 7 9, 6, 10 v ss v dd *inverter omitted in mc14023b 2, 5, 9, 12 1, 6, 8, 13 2, 4, 12 1, 3, 11 v dd v dd v ss v ss 8, 5, 13 mc14011b, mc14081b one of four gates shown mc14023b, mc14073b one of three gates shown
mc14001b series http://onsemi.com 6 typical b ? series gate characteristics n ? channel drain current (sink) p ? channel drain current (source) - 40 c + 85 c + 125 c figure 2. v gs = 5.0 vdc figure 3. v gs = ? 5.0 vdc 1.0 3.0 5.0 4.0 2.0 0 1.0 3.0 5.0 4.0 2.0 0 v ds , drain-to-source voltage (vdc) - 1.0 0 0 t a = - 55 c figure 4. v gs = 10 vdc figure 5. v gs = ? 10 vdc 16 14 12 10 8.0 6.0 4.0 2.0 0 5.0 3.0 1.0 10 8.0 6.0 4.0 2.0 0 0 0 figure 6. v gs = 15 vdc figure 7. v gs = ? 15 vdc 0 0 0 0 - 40 c + 25 c + 85 c + 125 c - 1.0 - 3.0 - 5.0 - 4.0 - 2.0 v ds , drain-to-source voltage (vdc) t a = - 55 c + 25 c t a = - 55 c - 40 c + 25 c + 85 c + 125 c v ds , drain-to-source voltage (vdc) v ds , drain-to-source voltage (vdc) v ds , drain-to-source voltage (vdc) v ds , drain-to-source voltage (vdc) t a = - 55 c - 40 c + 25 c + 85 c + 125 c 18 20 9.0 7.0 - 5.0 - 3.0 - 1.0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 - 9.0 - 7.0 - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5.0 - 45 - 50 10 6.0 2.0 20 16 12 8.0 4.0 18 14 t a = - 55 c - 40 c + 25 c + 85 c - 10 - 6.0 - 2.0 - 20 - 16 - 12 - 8.0 - 4.0 - 18 - 14 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 - 90 - 100 40 35 30 25 20 15 10 5.0 45 50 t a = - 55 c - 40 c + 25 c + 85 c - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10 i , d drain current (ma) i , d drain current (ma) i , d drain current (ma) i , d drain current (ma) i , d drain current (ma) i , d drain current (ma) + 125 c + 125 c these typical curves are not guarantees, but are design aids. caution: the maximum rating for output current is 10 ma per pin.
mc14001b series http://onsemi.com 7 typical b ? series gate characteristics (cont?d) voltage transfer characteristics figure 8. v dd = 5.0 vdc figure 9. v dd = 10 vdc 1.0 3.0 5.0 4.0 2.0 0 1.0 3.0 5.0 4.0 2.0 0 0 0 v in , input voltage (vdc) single input nand, and multiple input nor, or single input nor, or multiple input nand, and single input nand, and multiple input nor, or single input nor, or multiple input nand, and 2.0 6.0 10 8.0 4.0 2.0 6.0 10 8.0 4.0 v in , input voltage (vdc) v , out output voltage (vdc) v , out output voltage (vdc) figure 10. v dd = 15 vdc 0 0 single input nand, and multiple input nor, or single input nor, or multiple input nand, and 2.0 6.0 10 8.0 4.0 2.0 6.0 10 8.0 4.0 v in , input voltage (vdc) 12 14 16 v , out output voltage (vdc) dc noise margin the dc noise margin is defined as the input voltage range from an ideal ?1? or ?0? input level which does not produce output state change(s). the typical and guaranteed limit values of the input values v il and v ih for the output(s) to be at a fixed voltage v o are given in the electrical characteristics table. v il and v ih are presented graphically in figure 11. guaranteed minimum noise margins for both the ?1? and ?0? levels = 1.0 v with a 5.0 v supply 2.0 v with a 10.0 v supply 2.5 v with a 15.0 v supply figure 11. dc noise immunity v out v o v o v il 0 v ih v in v dd v dd v out v o v o v il 0 v ih v in v dd v dd (a) inverting function (b) non ? inverting function v ss = 0 volts dc
mc14001b series http://onsemi.com 8 ordering information device package shipping ? mc14001bcpg pdip ? 14 (pb ? free) 25 units / rail mc14001bdg soic ? 14 (pb ? free) 55 units / rail nlv14001bdg* mc14001bdr2g soic ? 14 (pb ? free) 2500 units / tape & reel nlv14001bdr2g* mc14001bdtr2g tssop ? 14 (pb ? free) nlv14001bdtr2g* mc14001bfelg soeiaj ? 14 (pb ? free) 2000 units / tape & reel mc14011bcpg pdip ? 14 (pb ? free) 25 units / rail MC14011BDG soic ? 14 (pb ? free) 55 units / rail nlv14011bdg* mc14011bdr2g soic ? 14 (pb ? free) 2500 units / tape & reel nlv14011bdr2g* mc14011bdtr2g tssop ? 14 (pb ? free) nlv14011bdtr2g* mc14011bfg soeiaj ? 14 (pb ? free) 50 units / rail mc14011bfelg 2000 units / tape & reel mc14023bcpg pdip ? 14 (pb ? free) 25 units / rail mc14023bdg soic ? 14 (pb ? free) 55 units / rail mc14023bdr2g soic ? 14 (pb ? free) 2500 units / tape & reel nlv14023bdr2g* mc14023bfelg soeiaj ? 14 (pb ? free) 2000 units / tape & reel mc14025bcpg pdip ? 14 (pb ? free) 25 units / rail mc14025bdg soic ? 14 (pb ? free) 55 units / rail nlv14025bdg* mc14025bdr2g soic ? 14 (pb ? free) 2500 units / tape & reel nlv14025bdr2g* mc14025bfelg soeiaj ? 14 (pb ? free) 2000 units / tape & reel
mc14001b series http://onsemi.com 9 ordering information device shipping ? package mc14071bcpg pdip ? 14 (pb ? free) 25 units / rail mc14071bdg soic ? 14 (pb ? free) 55 units / rail nlv14071bdg* mc14071bdr2g soic ? 14 (pb ? free) 2500 units / tape & reel nlv14071bdr2g* mc14071bdtg tssop ? 14 (pb ? free) 96 units per rail mc14071bdtr2g 2500 units / tape & reel nlv14071bdtr2g* mc14073bcpg pdip ? 14 (pb ? free) 25 units / rail mc14073bdg soic ? 14 (pb ? free) 55 units / rail mc14073bdr2g soic ? 14 (pb ? free) 2500 units / tape & reel mc14081bcpg pdip ? 14 (pb ? free) 25 units / rail mc14081bdg soic ? 14 (pb ? free) 55 units / rail nlv14081bdg* mc14081bdr2g soic ? 14 (pb ? free) 2500 units / tape & reel nlv14081bdr2g* mc14081bdtr2g tssop ? 14 (pb ? free) nlv14081bdtr2g* mc14082bcpg pdip ? 14 (pb ? free) 500 units / tube mc14082bdg soic ? 14 (pb ? free) 55 units / rail nlv14082bdg* mc14082bdr2g 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable.
mc14001b series http://onsemi.com 10 package dimensions soic ? 14 nb case 751a ? 03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc14001b series http://onsemi.com 11 package dimensions tssop ? 14 case 948g issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc14001b series http://onsemi.com 12 package dimensions pdip ? 14 case 646 ? 06 issue p 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m ??? 10 ??? 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ? t ? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 mc14001b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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